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Features
* * * * * * * * * * *
Full-Frame Image Sensor 4096 x 4096 Pixels 11 m x 11 m Photo-MOS Pixel with 100% Aperture Image Zone: 45 x 45 mm Frame Readout Through One, Two or Four Outputs Data Rates Up to 4 x 40 MHz (Compatibility with 7, 4 Frames/Second) True 12-bit High Dynamic Range Very Low Readout Noise Very Low Dark Current (MPP Mode) Optimized Resolution and Responsivity in the 400 - 1100 nm Spectrum On-chip Thermometer for Each Quarter Additional Full-Frame Operating Modes: - 4/3 Aspect Ratio: 4096 x 3072 - 2/1 Aspect Ratio: 4096 x 2048 - Binning 2 x 2 Pixels (Format 2048 x 2048 Pixels of 22 x 22 m) - Binning 4 x 4 Pixels (Format 1024x 1024 Pixels of 44 x 44 m) * On-request Frame Transfer Architecture: - 2048 Active Lines, One Memory Zone with Frame Readout Through One or Two Outputs - 2048 Active Lines, Two Memories Zones with Frame Readout Through Two or Four Outputs
16 M-Pixels Sensor AT71201M Preliminary
Applications
Flexibility and performance makes this device suitable for digital photography, graphic arts, medical or industrial applications and scientific analysis.
Description
Atmel's AT71201M is a full-frame sensor based on charge-coupled device (CCD) technology. It can be used in a wide range of applications thanks to operating mode flexibility, very high definition and high dynamic range. The nominal photosensitive area is made up of 4096 x 4096 useful pixels and is split into four independent zones that are driven separately by four independent four-phase clock sets. Thus the sensor can be used in up to 12 main modes. The large format and high definition make the device suitable for any application requiring precision. The high sensitivity of the 11 x 11 m pixels with 100% fill factor provides a large bandwidth of response with up to 1100 nm wavelength. Two serial registers and four independent output amplifiers offer a high-frequency functionality at 40 MSPS and up to 7.4 frames per second with a high signal to noise ratio.
Rev. 5328A-IMAGE-05/03
1
Pinout
Figure 1. AT71201M Pinout, Top View of the Sensor
2
2
25
24
1 A
A B Output 3 Output 1 VS1 C VOS1 PHILS1 VTHH1 PHILA6 PHILA5 PHITA VSS2 PHIPB1 PHIPA1 PHIPA3 PHIPB3 VSS2 VSS1 PHILA1 PHILA2 VTHH2 PHILS2 Output 2 VOS2 VS2 VDR2 24 VGS1 VTHL1 VSS2 PHILA8 PHILA7 VDEA PHIPB2 PHIPA2 PHIPA4 PHIPB4 PHIFCA PHILA3 PHILA4 VDE VTHL2 VGS2 VDD2 PHIR2 VSS3 25 VDD1 PHIR1 D
VSS2
VDR3
VDR1 VSS3
B
PHIR3
VS3
C
VDD3
VOS3
D
AT71201M
E B Zone A Zone D Zone C Zone F G H J K L M REGISTER B REGISTER A N
VGS3
PHILS3
E
VTHL3
VTHH3
F
VDE
PHILB2
G
PHILB4
PHILB1
H
PHILB3
VSS1
J
PHIFCB
VSS2
AT71201
K Output 4 2
PHIPC4
PHIPC3
L
PHIPD4
PHIPD3
M
PHIPD2
PHIPD1
N
PHIPC2
PHIPC1
P
P
VDEB
VSS2
Q
Q
PHILB7
PHITB
R
R
PHILB8
PHILB5
S
S
VSS2
PHILB6
T
T
VTHL4
VTHH4
U
U
VGS4
PHILS4
V
V
VDD4
VOS4
PHIR4
VS4
W
W
X
X
VSS2
VDR4
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AT71201M
Table 1. AT71201M Pinout
Signal Name PHILA [1;8] PHILB [1;8] PHILS [1;4] PHIR [1;4] PHIPA [1;4] PHIPB [1;4] PHIPC [1;4] PHIPD [1;4] PHITA VGS [1;4] VOS [1;4] VDD [1;4] VS [1;4] VDR [1;4] VDE (2) VDEA VDEB VTHL [1;4] VTHH [1;4] VSS (12) Parameter Registers A clocks Registers B clocks Summing clocks Reset gates Image zone A clocks Image zone B clocks Image zone C clocks Image zone D clocks Image zone to register A transfer clock Register output gate biases Video outputs Amplifier drains Amplifier sources Reset drains Peripheral vertical drain Peripheral drain along register A Peripheral drain along register B Thermometer low 1 to 4 Thermometer high 1 to 4 Ground connection
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Block Diagram
Figure 2. AT71201M Block Diagram - Top View
Ls1 VGS1 R1 VDR1 VS1 VOS1 VDD1 VTHH1 VTHL1
16 Prescans VDEA LA1 to 4 LA5 to 8
TA
VS2 VOS2 VDD2 VTHH2 VTHL2
Ls2 VGS2 R2 VDR2
TA
PAj
24 vertical references
PAj
PBj VDE
4096 x 4096 useful pixels (11 x 11 m) = 45 x 45 mm
PBj VDE
PCj 8 vertical & horizontal insulating elements (including 4 dark ones)
PCj
PDj
PDj
} } } }
A Zone
B Zone
C Zone
D Zone
TB
Ls3
VGS3
R3
VDR3
VS3 VOS3 VDD3 VTHH3 VTHL3
LB1 to 4 VDEB
LB5 to 8 VS4
Ls4
TB
Thermometer
VOS4 VGS4 VDD4 R4 VTHH4 VDR4 VTHL4
Readout modes
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Architectural Overview
General Parameters
Table 2. General Parameters
Parameter Pixel size Number of useful pixels per line Number of useful lines Number of extra lines Number of readout registers Number of prescan CCD stages (per output) Number of dark references (cells per line) Number of outputs (2 per register) MPP mode/low dark current mode Anti-blooming functionality Binning (summation) mode Pixel clocking mode Readout Register clocking mode Specific functions Notes: Value 11 x 11 m 4096 4096 8 per register 2 16 24 4(1) Yes (image zone) no Yes(2) 4-phase 2-phase Thermometer
1. The full-frame version can be read through one, two or four outputs 2. The lines summation into the register is made by a specific timing diagram. The integration time should be adapted to prevent charge overflow.
A specific clock allows column summation. The pixel size is 11 x 11m2 with 100% fill factor (photo-MOS technology). The sensor is compatible with a 180 rotation. The image zone commands are split in 4 horizontal areas. The combination of the Pij clocks allows various transfer configurations. The serial registers are driven by 8 Li clocks. An adapted combination of them allows transfers of 100% of stages to the right side or the left side or 50% in each direction.
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Organization
Top to Bottom The AT71201M is made up of four zones (A, B, C and D) that are separately driven. Table 3. Vertical Characteristics
Zone A 2048 active lines, 100% photosensitive B C D 8 dummy lines (4 photosensitive ones) 2048 active lines, 100% photosensitive 2048 active lines, 100% photosensitive 2048 active lines, 100% photosensitive Configuration 8 dummy lines (4 photosensitive ones)
Corner to Center Table 4. Horizontal Characteristics for Different Modes
Readout Mode Characteristic Prescan stages Dark references Insulating elements Useful pixels One Output 16 24 8 4096 Two Outputs on Same Register 16 24 8 2048
Output Amplifiers
The charge packets are clocked towards the output nodes and are converted to voltages. The potential at the output node is read through a source follower amplifier.
Figure 3. On-Chip Output Amplifiers
VDD
R
M1
M3
M5
Output node VOS
M2
M4
M6
VS
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Absolute Maximum Ratings(1)
Table 5. Maximum Applied Voltages with Respect to VSS
Signal Name PHILA [1;8] PHILB [1;8] PHILS [1;4] PHIR [1;4] PHIPA [1;4] PHIPB [1;4] PHIPC [1;4] PHIPD [1;4] PHITA PHITB Parameter Registers A clocks Registers B clocks Summing clocks Reset gates Image zone A clocks Image zone B clocks Image zone C clocks Image zone D clocks Image zone to register A transfer clock Image zone to register B transfer clock Min -0.3V -0.3V -0.3V -0.3V -15V & PHIPA [others] -15V -15V & PHIPB [others] -15V -15V & PHIPC [others] -15V -15V & PHIPD [others] -15V -15V & PHIPA [4] -15V -15V & PHIPB [4] -15V Max +15V +15V +15V +15V +15V & PHIPA [others] +15V +15V & PHIPB [others] +15V +15V & PHIPC [others] +15V +15V & PHIPD [others] +15V +15V & PHIPA [4] +15V +15V & PHIPB [4] +15V
VGS [1;4] VOS [1;4] VDD [1;4] VS [1;4] VDR [1;4] VDE VDEA VDEB VTHL [1;4] VTHH [1;4] VSS Note:
Ouput gates Video outputs Amplifier drains Amplifier sources Reset drains Peripheral drain Peripheral drain along register A Peripheral drain along register B Thermometer low 1 to 4 Thermometer high 1 to 4 Ground
-0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V
+15V +15V +15V +15V +15V +15V +15V +15V +15V +15V
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
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Shorting VOS to any other pin, even temporally, can permanently damage the output amplifier. Device exposure to ESD stress could result in current leakage or performance degradation; reliability can also be affected. To avoid degradation, sensors (including pins and package) have to be handled carefully using a grounded bracelet. When unplugged, they have to be stored in the original case (or box). In any case, pins of the devices must not be discharged straight to ground..
Storage Temperature Range Operating Temperature Range Thermal Cycling
-40C to +70C 0C to +70C 3C/mn
DC Characteristics
Table 6. DC Characteristics
Parameters Source bias Amplifier drain supply Substrate bias Reset diode Output gate Vertical drain Horizontal drain Notes: Symbol Vsi VDDi(1) Vss VDRi
(2)
Typical Value 0V 15V 0V 14V 3.5V 8V 12V
Adjusting Range [0;1] Volts [14.5;15.5] Volts
Current 4 x -25 mA 4 x 25 mA
[13.5;14.5] Volts [3;4] Volts [6;9] Volts (15 V max respect to Ti) [6;15] Volts
< 5 A < 5 A < 50 A < 50 A
VGSi VDE VDEi
1. If the associated output i is not used, VDDi should be stated to 0 Volts in order to reduce global power consumption 2. VDRi voltage should always be kept lower than VDDi voltage, especially during power on
Recommendation: All DC voltages should be bypassed by adding capacitors as closed as possible to the pin connection.
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Drive Clock Characteristics
Table 7. Drive Clock Characteristics
Parameter Image clocks Symbol PHIPij(1) State Low High Transfer clocks PHITk(2) Low High Register clocks PHILkm(2) Low High Summing clocks PHILSj(1) Low High Reset gate clocks Notes: PHIRj(1) Low High 1. i = A to D, j = 1 to 4 2. k = A to B, m = 1 to 8 Minimum -9V +2.5V -6V +2.5V 0V +7V 0V +7V 0V +11V Typical -8V +3V -5V +3V 0V +7.5V 0V +7.5V +2V +12V Maximum -7.5V 37 nF +3.5V -4V 200 pF +3.5V 0.5V 180 pF +8V 0.5V 15 pF +8V +3V 15 pF +13V Typical Capacitance
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Operating Modes
Figure 4. Operating Modes
4112 transfers min NBV = 4112
1-2-3 modes
PA1=PB1=PC1=PD1= PA4=PB4=PC2=PD2= PA3=PB3=PC3=PD3= PA2=PB2=PC4=PD4=
TA = Low Level
For the required readout mode, the vertical and horizontal clocks must be tied together, as following:
VERTICAL TRANSFER 4112 transfers min 2056 transfers min NBV = 4112 NBV = 2056
4-5-6 modes 7-8-9 modes
P1 P2 P3 P4 PA1=PB1=PC1=PD1= PA2=PB2=PC2=PD2= PA3=PB3=PC3=PD3= PA4=PB4=PC4=PD4=
TA = P1 TB = P1
3080 transfers min NBV = 3080
10-11-12 modes
PA1=PB1=PC1=PD1= PA2=PB4=PC2=PD2= PA3=PB3=PC3=PD3= PA4=PB2=PC4=PD4=
TA = P1 TB = P1
P1 P2 P3 P4
PA1=PB1=PC1=PD1= PA2=PB2=PC4=PD4= PA3=PB3=PC3=PD3= PA4=PB4=PC2=PD2=
TA = P1
P1 P2 P3 P4
P1 P2 P3 P4
TB = P1
TB = Low Level
Symbols P1, P2, P3, P4 correspond to the clocks described in the full-frame mode timing diagrams. Abbreviations NBV and NBH correspond respectively to the vertical and horizontal number of transfers. The unused horizontal clocks (L, R, LS) must be stated to their higher level.
1
Inactive
2
1
2
1
2
1
2
4144 PIXELS PERIODS NBH = 4144
4-7-10 modes 1-7-10 modes
LA1=LA4=LA5=LA7=L1 LA2=LA3=LA6=LA8=L2
Mode1
Mode4
Mode7
Mode10
HORIZONTAL TRANSFER
3 1 Inactive
4 2
3 1
Inactive
4 2
3 1
4 2
3 1
4 2
LB1=LB3=LB5=LB8=L1 LB2=LB4=LB6=LB7=L2
4144 PIXELS PERIODS NBH = 4144
LA1=LA3=LA5=LA8=L1 LA2=LA4=LA6=LA7=L2
Mode2
Mode5
Mode8
Mode11
5-8-11 modes 2-8-11 modes
3 1 Inactive
4 2
3 1
Inactive
4 2
3 1
4 2
3 1
4 2
LB1=LB4=LB5=LB7=L1 LB2=LB3=LB6=LB8=L2
2096 PIXELS PERIODS NBH = 2096
6-9-12 modes
LA1=LA4=LA5=LA8=L1 LA2=LA3=LA6=LA7=L2
Mode3
Mode6
Mode9
Mode12
3
4
3
Inactive
4
3
4
3
4
LB1=LB3=LB5=LB7 =L1 LB2=LB4=LB6=LB8=L2
3-9-12 modes
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Timing Diagrams
Figure 5. Full-Frame Mode Timing Diagram
PHIP1 PHIP2 PHIP3 NBH pulses PHIP4 PHITk PHIL1 PHIL2
(2) (2)
PHILSj PHIRj
... cleaning
Integration time
Readout time (NBV pulses)
Cleaning ...
Figure 6. Line Timing Diagram
(1)
Period Tv = 9 x T0
PHIP1 PHIP2 PHIP3 PHIP4 PHITk = PHIP1 PHIL1 PHIL2
(2) (2)
PHILSj PHIRj
Notes:
1. T0 = Master clock period (vertical transfer) 2. See Figure 4
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Figure 7. Summation Timing Diagram of 2 Lines
Period Tv = 15 x T0
(1)
PHIP1 PHIP2 PHIP3 PHIP4 PHITk = PHIP1 Line summation PHIL1 PHIL2
(2) (2)
PHILSj PHIRj
Figure 8. Readout Signal
PHIP1 PHIP2 PHIP3 PHIP4 Period = FH -1
(3)
PHITk
PHIL1 PHIL2
(2) (2)
PHILSj PHIRj VOSj
Reset/reference/signal levels
Notes:
1. T0 = Master clock period (vertical transfer) 2. See Figure 4
3. FH = Readout Register Frequency
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AT71201M
Figure 9. Summation Timing Diagram
PHIP1 PHIP2 PHIP3 PHIP4 PHITk
(1) (1)
PHIL1 PHIL2
PHILSj PHIRj Column summation
VOSj
Reset/Reference/Signal levels
Note:
1. See Figure 4
Figure 10. Frame Transfer Sequence
Readout time
Exposure Time
1 Line Transfer
Y Lines Summation
x Columns Summation
1 Stage Transfer
(Y-1) times Yes
(X-1) times Yes
Cleaning Period
Lines Summation
Columns Summation
c-1 times l-1 times
The readout sequence corresponding to an image made of C x l pixels * * * * XC = 2048 in modes 3, 6, 9, 12 XC = 4096 in other modes Yl = 2048 in modes 1 to 6 Yl = 4096 in modes 7 to 9
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Table 8. Time Constants of Different Phases
Time Buffer time = Waiting time between Pij and Lkm acting Rise Time and Fall Time of Pij, Tk Rise Time and Fall Time of Lkm, LSj Rise Time and Fall Time of Rj Symbol Tb Ts Tq Tr Minimum 100 ns 250 ns 3 ns 1.5 ns Typical 0.5 x T0 6 ns 3 ns Maximum 0.5 x T0 -
T0 = master clock period (vertical transfer)
Frame Rate Characteristics
Figure 11. Frame Rate Characteristics
14 12 10
Frame/sec
8 6 4 2 0 0 20 40 60 80 100 Integration Time (ms)
1 Output 2 Output 4 Output 4 Outputs (2 x 2 binning)
Frame rate is given for maximum readout frequency(1).
Note: 1. Horizontal pixel frequency, FH = 40 MHz Vertical transfer time, To = 1.5 s Buffer time, Tb = 100 ns
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Output Buffer
Table 9. Output Buffer(2)
Parameter DC output Output impedance Output amplifier supply current(1) Amplifier bandwidth (-3 dB) Charge to Voltage Conversion factor Temperature conversion Vertical transfer time Readout register frequency Note: 1. Per output 2. All characteristics given for temperature = 25C Symbol Vref Zout IDD BW CVF VTH T0 FH Minimum 8.0 - 19 - - - 1.5 - Typical 8.6 88 25 200 6.0 7.5 2 - Maximum 9.2 - 31 - - - - 40 Unit V mA MHz V/ electron mV/C s MHz
Electro-Optical Performances
Table 10. Electro-Optical Performances(3)
Parameter Pixel saturation voltage Readout saturation charge in binning mode Dynamic range Readout noise Responsivity Resolution (MTF) at 45 cycles/mm - H axis Resolution (MTF) at 45 cycles/mm - V axis Pixel response non-uniformity Image zone dark signal, MPP Image zone dark signal, non-MPP Register dark signal, non-MPP Image zone dark signal non-uniformity, MPP integration Horizontal charge transfer efficiency per CCD stage Vertical charge transfer efficiency per CCD stage Notes: 1. Combined with 2 mm "BG38" IR filter type 2. Standard deviation 3. All values given at 25C, typical voltages Symbol VSAT RSAT DR RN R MTFX MTFY(1) PRNU(1)(2) DS1 DS2 DSR DSNU(2) HCTE VCTE
(1)
Minimum 600 - 72 - 3.8 - - - 0.05 10 30 - 0.99993 0.99995
Typical 750 1800 74 25 4.2 45 50 0.5 0.2 20 60 0.5 0.99998 0.99998
Maximum 900 - 76 - - - - 3 2 40 100 1.5 - -
Unit mV mV dB electron V/(J/cm) % % % mV/s mV/s mV/s mV/s - -
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Figure 12. Spectral Responsivity
14 12 Responsivity (V/J/cm) 10 8 6 4 2 0 400 500 600 700 800 900 1000 1100
Wavelength (nm)
Temperature Measurement
A current of 100 A is forced between VTHLi and VTHHi, in the range of 0 to 70C, the corresponding measured voltage, is proportional to temperature:
Temperature(C ) =
VTHHi (mV ) - VTHLi (mV ) - 613(C ) 7.5(mV / C )
Relative thermometer accuracy is 0.13C/mV 10%
Absolute thermometer precision is 10C. Figure 13. On Chip Thermometer
VTHHi
Resistor
VTHLi
I forced
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AT71201M
Image grade
Table 11. Image Grade(2)
Grade Blemishes Total E Notes: 1500 D-min 3
(1)
Cluster 1 Total 100 D-min 50
(1)
Cluster 2 Total 20 D-min 100
(1)
Column Total 10 D-min(1) 150
1. D-min: distance of pixels defects in any direction. All occurrences are non-contiguous. 2. Testing has been carried out under the following conditions: Operating temperature = 25 C Illumination conditions: 3200K Halogen lamp with BG38 Infrared filter and f/3.5 aperture Integration time in darkness = 10 seconds, test under illumination at 50% of VSAT Standard mode, To = 1.5 s, FH = 40 MHz
Definitions
Table 12. Defect Sizes
Type Blemish Cluster Column Description 1 x 1 pixel defect Blemish groupings of less than a given number of adjacent defects: 1 x 1 pixel < cluster 1 size 2 x 2 pixels 2 x 2 pixels < cluster 2 size 5 x 5 pixels One-pixel-wide column with more than seven contiguous defective pixels
Table 13. Defects in Darkness
Type Blemish/Clusters Column Description Pixel signal deviation of more than 200 mV from the average output signal Column signal deviation of more than 50 mV from the average output signal
Table 14. Defects Under Illumination
Type Blemish/Clusters Column Description Pixel signal deviation of more than 30% from the average output signal Column signal deviation of more than 20% from the average output signal
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Ordering Information
1 2 3 4 5 6 7 8 9 10 11 AT71201 Customer specification Technological variant Temperature range: C: 0C to +70C Quality assurance level
Package family: R: Pin Grid Array (PGA)
Options: B = Mechanical mask E = On chip color filters
Image grade: E: Standard H: High
Package variant: N: Non-sealed window R: Anti-reflective glass window
The following part numbers are available: * * AT71201MCRER AT71201MCREN
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Package Drawing
71.00 0.8 61.80 0.7 55.80 0.6 35.5 0.4 6. 1. 0.46 0.05
68.0 0.7 6.
35.5 0.4
First Pixel
Y = 12.970 0.2
5. 8.5 0.8 X = 12.970 0.2
6. 54.0 0.5
6.
1.00 0.01
5.66 0.5
REFERENCE (Ring) Zopt. = 1.1 0.08 Zmech. = 0.7 0.05 (See note 3. - 4.) 2. 1.1 0.1 (Window) 2.06 0.2 2.5 0.25 4.57 0.25
53.34 0.55 5. 2.54 Typ. 2.54 Typ.
1 2
60.96 0.6 55.88 0.6
Notes: 1. Anti-reflective window 400 - 700 nm 2. Photosensitive area 3. Zopt = Optical distance between REFERENCE surface and 2 4. Zmech = Mechanical distance between REFERENCE surface and 2 5. Pin A1 index mark 6. Mechanical references/die positionning (first pixel) REFERENCE: Z REFERENCE: XY All Dimensions In Millimeter Die Flatness 50 m Die Axis Angle 0.2 24 25
A B C D E F G H J K L M N P Q R S T U V WX
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